Dr. Kiran Bailey

Dr. Kiran Bailey

Assistant Professor

Ph.D (ELECTRONICS-VLSI)

kiran.ece@bmsce.ac.in

Research Interests: Design and characterization of Novel CMOS Devices such as FinFETs and Multiple-gate MOSFETs

About

A dedicated and hardworking academician with over 25 years of experience in BMS College of Engineering, having vast experience in curriculum design, lab set up and Industry interaction. She has more than 40 publications to her credit and has also filed for patents. She is currently guiding 4 Ph.D scholars and is involved in procuring
government funding for research projects in association with Industry. She is involved with setting up of Network Embedded Lab and Incubation center in the department to encourage Product innovation by the students.
She has also set up a research lab on Nano sensor design and fabrication in collaboration with Dept. of Chemistry, BMSCE.

Education

  • Ph.D - VLSI
    UVCE, Bangalore University
    Passed Year: 2014 | Program Type: PartTime

Selected Publications

  • Journal | Published On : 09-07-2022
    Dr. Kiran Bailey, Prof. K. Sujatha, Dr. Srinidhi Raghavan
    Nanocrystalline Spinel CoFe2O4 Thin Films Deposited via Microwave?Assisted Synthesis for Sensing Application” Journal of Electronic Materials, Springer , https://doi.org/10.1007/s11664-022-09789-z , Accepted: 21 June 2022, Published online : 9 July 2022
    Weblink
  • Journal | Published On : 31-07-2020
    Manjushree B Somasagar, Dr. Kiran Bailey
    Manjushree B Somasagar, Dr. Kiran Bailey, “CLEFIA- A Encryption Algorithm using Novel S-Box Architecture”, International Journal of Engineering Research & Technology (IJERT), Vol. 9 Issue 07, July-2020, ISSN: 2278-0181, PP. 825-827
    Weblink
  • Journal | Published On : 30-06-2020
    Apoorva H M, Dr. Kiran Bailey
    Apoorva H M, Dr. Kiran Bailey, “UVM based Design Verification of FIFO”, International Journal of Engineering Research & Technology (IJERT), Vol. 9 Issue 06, June-2020, ISSN: 2278-0181, PP. 774-776.
    Weblink
  • Journal | Published On : 31-05-2020
    A.Vipula, Nikkitha.N , Dr Kiran Bailey , Loganath Ramachandran
    A.Vipula, Nikkitha.N , Dr Kiran Bailey , Loganath Ramachandran, “Developing Verification IP (VIP) for AMBA LowPower Interface P-Channel Protocol using Universal Verification Methodology (UVM)”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE), Volume 9, Issue 5, May 2020, e-ISSN: 2278 – 8875, PP. 1107-1115
    Weblink
  • Journal | Published On : 31-12-2018
    Bhagyashree K , Dr. Kiran Bailey, Dr.Rangaswamy, K Sujatha
    Bhagyashree K , Dr. Kiran Bailey, Dr.Rangaswamy, K Sujatha, “TCAD Device Design and Analysis of 20nm DGTFET”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 7, Issue 12, December 2018, ISSN (Online): 2278 – 8875
    Weblink
  • Journal | Published On : 30-09-2018
    Sushmita Badiger, K.Sujatha , Dr. Kiran Bailey
    Sushmita Badiger, K.Sujatha , Dr. Kiran Bailey, “Homojunction TFET Device Design and Analysis for Low Power Applications”, IJAREEIE, Volume 7, Issue 9, September 2018, ISSN: 2278 – 8875
    Weblink
  • Conference | Published On : 02-09-2015
    Dr.Kiran Bailey, Rafeek Alas
    "Design Space Exploration of 14 nm Gate All Around MOSFETs", 2015 Fifth International Conference on Advances in Computing and Communications (ICACC),pp. 469-472
    Weblink
  • Journal | Published On : 31-05-2014
    Dr.Kiran Bailey, Dr.K.S. Gurumurthy, Nagarathna Shanbhag
    “Process Variability Analysis in 14-nm FinFET Inverter”, International Journal of Science, Engineering and Technology Research IJSETR, Vol. 3, Issue 5, May 2014.
    Weblink
  • Journal | Published On : 30-10-2012
    Dr.Kiran Bailey, Dr.K.S. Gurumurthy
    “3D device modeling and assessment of Triple gate SOI FinFET for LSTP applications”, International Journal of Computer Theory and Engineering, IJCTE, Vol. 4, No. 5, October 2012, pp. 831-834, ISSN: 1793-8201.
    Weblink
  • Journal | Published On : 30-10-2012
    Dr.Kiran Bailey, Dr.K.S. Gurumurthy,A. Prathima
    “IMPACT OF DEVICE PARAMETERS OF TRIPLE GATE SOI-FINFET ON THE PERFORMANCE OF CMOS INVERTER AT 22 nm”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012, pp.79-91. ISSN: 0976 - 1357 (Online); 0976 - 1527 (print).
    Weblink
  • Journal | Published On : 30-10-2010
    Dr.Kiran Bailey, Dr.K.S. Gurumurthy
    "Modeling and Performance evaluation of UTB SGOI Devices scalable to 22 nm Technology node“, WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Volume 9,Issue 10, October 2010, pp. 607-616, ISSN: 1109-2734
    Weblink
  • Journal | Published On : 22-07-2010
    Dr.Kiran Bailey, Dr.K.S. Gurumurthy
    "Low Power Semiconductor devices at 65 nm technology node", INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING , Volume 4, Issue 2, 2010, pp. 43-51,ISSN: 1998-4464
    Weblink

Other Information

MOU’S Signed With Blr Labs And Tequed Labs.
Ongoing Consultancy With Tequed Labs.

Ongoing funded Project :
1. Research project funded by FRPS for Rs. 2 Lakhs titled "Cubic Spinel Ferrites for toxic gas sensing at sub-ppm concentrations".
2. Co-CI in C2S project “Design and Development of Ground-penetrating RADAR with On-field Reconfiguration Capacity Applicable to Sustainable Industrial and Agricultural Purposes” funded by MeitY for Rs.70 Lakhs.

Completed funded Projects :
1. 'Smart Department Implementation using IOT'
Department of ECE, BMSCE in collaboration with Industry TEQUED LABS AND Mentee institution - FET MJPRU, Bareilly received finanacial support of Rs.1,96,000/- through TEQIP III under Twinning-1.3; Component head 1.3.2.7-Twinning/Mentoring on 23/8/2019.
2. Setting up of "Hi-Tech Network Embedded Lab and the Incubation Center" in ECE Department with 48 systems, Embedded boards and related Software through TEQIP III Funding of Rs. 37 Lacks.
3. ‘Investigation of Gas Sensor Properties of substituted Spinel Ferrite Gas Sensors’
Department of Electronics & Communication Engineering in association with Department of Chemistry were awarded seed money for R & D activity under Centre of Excellence in Advanced Materials Research - TEQIP-III -1.3: on 20/2/2021
Dr. Kiran Bailey and Prof. K. Sujatha from ECE and Dr. Srinidhi .M from Dept. of Chemistry received Rs.69,000/- for project
Major collaborative activities with various Industry partners:
1. Wafer Space, Bangalore: Conducted 4 week Internship program on Fundamentals of Physical Design from 18/7/2018 – 14/08/2018 for 7th Sem EC Students to enable them to develop skills on PD. Outcome- Nearly 50% of the participants got placed in core domain.
2. BLR Labs, Bangalore: MOU Signed with BLR Labs, Bangalore. Outcome- The Student ID verification prototype under development since April 2018.
3. TEQUED Labs, Bangalore: Skill Development Programs in the latest cutting-edge technologies organized in the college for Faculty and Students since June 2017. MOU Signed with TEQUED Labs, Bangalore on 7/12/2018 to set up Hi-Tech Network Embedded Lab and Incubation Centre in the department. The main Objective of the Incubation centre is to provide/enhance skills required for the Industry and also to promote Entrepreneurs in the student community. The focus is to train the students and Faculty in the relevant domain and also to help them in developing their product. TEQUED Labs will mentor the students and Faculty to develop their prototype, file patents, Support for registering their company, Apply for Govt. funding and also to Market their products.
The Activities conducted and outcomes under the Incubation Center :
• 2 day Skill Development program on “Fundamentals of Machine Learning and Artificial Intelligence on 23/3/2019 and 24/3/2019.
• 2 Week FDP on “IOT and its Applications”- 24/6/2019 -5/7/2019.
• Internship Program for students during Jan 2019.
• Execution of Phase-1 of Joint Research and Development Project Collaboration with Industry and Mentee Institution FET MJPRU, Bareilly under TEQIP-III.
• Opening of “Centre of Global Certifications” during November 2020.
• Joint Patent on “Radio Frequency Identification Based User Database Management System” filed on 28/6/2019 and the patent application no.201941025817 is published in Journal No.01/2021, Journal date: 01-01-2021-IPO.
• 2 More Prototypes under development in the Incubation centre.
• Application for Govt. Funding for the development of Incubation centre under Process.
4. Cisma Consultants Pvt Ltd, Bangalore: Skill Development and Internship Program on “Verification Methodology with SystemVerilog and UVM” during the period 06th July 2019 to 03rd August 2019. Outcome- More than 50% of the participants got placed in core domain.
5. 2 patents filed


Resource Person for:
2 Week TEQIP III Sponsored Faculty Development Program on “IOT and its Applications”- 24/6/2019 -5/7/2019.

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