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Dr. Jeeru Dinesh Reddy

Dr. Jeeru Dinesh Reddy

Assistant Professor

B.E, M.E, Ph.D

dineshreddy.ece@bmsce.ac.in

Research Interests: ASIC Design and Verification, FPGA based programmable SoCs, Physical Unclonable Function (PUF) based authentication

About

Ph.D. in VLSI Design from National Institute of Technology, Surathkal , Karnataka (2018-2023)
Masters in Engineering from Anna University , PSG College of Technology , Coimbatore.In the Department of Electronics and Communication Engineering , specialised in VLSI Design (2003-2005).
Bachelors in Engineering from Andhra University , GITAM College of Engineering , Visakhapatnam. In the Department of Electronics and Communication Engineering ((1999-2003)

Experience in VLSI industry from 2005:

ASIC Design Engineer at TTM India Pvt. Ltd. Hyderabad (2005-2006).
ASIC/SoC Design Verification Engineer at Wipro Technologies, Bangalore (2006-2010).
Technical Consultant in ASIC Design at Calligo Technologies Pvt. Ltd (2015 to 2016)
Consulting Technical Manager @ SiValley Technologies (2016 to 2018)
Subject Matter Expert in Verification @ Ignitarium Technology Solution Pvt. Ltd (2021 to 2022)
Mentor @Coreel Technologies (2020 to 2021)
Assistant Professor at BMS College of Engineering, Bangalore (2010 - till date).



https://www.linkedin.com/in/jeeru-dinesh-reddy-54346116/


Industry Interaction:
1.Calligo Technologies Pvt. Ltd. (Jun'15 - Jun'16)
Domain of work: Developed a Multicore verilog simulator, that helps in reducing the simulation time and thus improving the verification time on a Sytem on Chip.
2. SIvalley Technologies Pvt Ltd,
Domain of Work: FPGA prototyping of 5G modem using an OTN processor and deploying my research work on PUF implementation using FPGAs on the said module. work carried out at Wipro Technologies (Dec'17-Mar'18)
3. CoreEL technologies (Jan'19-March'19)
Domain of Work: Design and Development of Physical Unclonable Function
4. Ignitarium Tehcnologies Pvt.Ltd(June'21 -Feb'22)
Domain of work : Training consultant
5. Intel Technologies Pvt.Ltd (Jul'22-Nov'22)
Domain of work : RTL Design and formal verification

Education

  • VLSI - Electrical and Electronics Engineering - VLSI
    National Institute of Technology Surathkal
    Passed Year: 2020 | Program Type: FullTime
  • VLSI - Electronics and Communication Engineering - VLSI
    Anna University
    Passed Year: 2005 | Program Type: FullTime
  • Bachelor of Engineering - ECE
    Andhra University
    Passed Year: 2003 | Program Type: FullTime

Selected Publications

  • Conference | Published On : 15-09-2020
    J Dinesh Reddy
    Implementation of Enhanced Parallel port interface for Frequency analysis in a configurable Ring Oscillator PUF circuits on Xilinx Spartan 3E architecture Jeeru, D.R., Vittal, K.P., Anikethan, H.V.U., Kumar, A.S. 2019 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2019, 2019, 9012874
    Weblink
  • Journal | Published On : 25-08-2020
    J Dinesh Reddy
    Design and modelling an attack on multiplexer based physical unclonable function Venkata, A.M., Jeeru, D.R., Vittal, K.P. SSRG International Journal of Engineering Trends and Technology, 2020, 68(6), pp. 63–67
    Weblink

Other Information

IEEE-VLSI, IEEE-TIE, IESA, IEEE Blended Learning Program

Consultancy works: Chip-Edge Technologies (Training to bridge the industry-academia gap)

Calligo Technologies Pvt. Ltd (Handling Development with respect to Multicore support to CAD tools)

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