Faculty Profile

About

Dr. Vasundhara K S, obtained her Bachelor’s degree (ECE) from JNN College of Engg, Shimoga (Mysore University) in 1989, M. Tech from B.M.S. College of Engg. in 2002, Ph.D in Electronics Engg. from Bangalore University in 2012. Joined BMSCE during 1999, has teaching experience of 25 years and 3 years of Industrial experience in analog design from ELTEL (Electronics and Telecommunications) industries Bangalore. She is also contributing as Principal Investigator for the project “Design and Development of Ground-penetrating RADAR with On-field Reconfiguration Capacity Applicable to Sustainable Industrial and Agricultural Purposes”, Chip to start up program under MeitY with the Fund of Rs. 80 Lakhs for 3 years. Projects under TEQIP-2, with the fund amount of Rs.10 Lakhs for setting up of state of the art VLSI lab. She has Established Centre of Excellence with Rs. 25 lacks funds from ESSCI (Electronic Sector Skill Council of India). She has published over 70 research papers and current research includes Analog design using GaN, Digital Circuit design using GNR, CNTFETs, FDSOI. Patent granted for the Invention “Capless LDO (Low Dropout Regulator) With Programmable Output Voltage”. “Method and System for Arithmetic Circuits in quaternary Logic”. She is guiding two research scholars allotted to her through AICTE National Doctoral Fellowship Scheme (NDF). Organized numerous National International conferences, workshops, guest lectures, on campus Internships for professional development of the department with industry collaboration. Program Coordinator for PG ‘VLSI Design and Embedded Systems’ as well as PG NBA activity. Member AC, DAC, BOE, BOS for BMSCE, Interacting with outside world as Session chair, project evaluator, doctoral committee, BOE and BOS member also as resource person.
She is Senior Member IEEE, Fellow IETE and Life Member IMAPS India, ISTE, IACSIT.

Education

• Ph.D - ELECTRONICS ENGINEERING
  BANGALORE UNIVERSITY
  Passed Year: 2012 | Program Type: PartTime
• M.TECH. - ELECTRONICS ENGINEERING
  B.M.S.C.E./V.T.U.
  Passed Year: 2002 | Program Type: FullTime
• B.E. - ELECTRONICS AND COMMUNICATION ENGINEERING
  JNNCE/MYSORE UNIVERSITY
  Passed Year: 1989 | Program Type: FullTime

Selected Publications

• Conference | Published On : 06-01-2024
  K. S. Vasundhara Patel, Bhukya Balaji Naik, Y. M. Sandesh, Naveen Kumar,
  “Implementation of the AES Algorithm on FPGA” Lecture Notes in Electrical Engineering 1105N, Advances in Communication and Applications, Proceedings of ERCICA 2023, Volume 2
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• Journal | Published On : 12-08-2023
  Vasundara Patel K S, Niranjan Kumar (1BM19LVS12)
  Journal of Circuits, Systems, and Computers (JCSC)’ Vol 32 No. 12 “Design and Simulation of Low Dropout, Low Power Capless Linear Voltage Regulator”
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• Book Chapter or Books | Published On : 28-12-2022
  Vasundara Patel K S, Tulasi Naga Jyothi Kolanti
  “Design and Performance Analysis of Quaternary GNRFET Storage Cell” Springer Lecture Notes in Networks and Systems book series (LNNS, volume 554), pp 497–504. First Online: 28 January 2023
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• Journal | Published On : 12-12-2022
  Vasundara Patel K S, BHUKYA BALAJI NAIK
  “Development Of Medium Access Control Scheme For Multihop Cellular Networks” Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition), ISSN:1671-5497, E-Publication Online Open Access, Vol: 41 Issue: 12-2022
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• Conference | Published On : 18-08-2022
  Vasundara Patel K S, Tulasi Naga Jyothi Kolanti, Yathish D G
  “An efficient design of GNRFET based quaternary logic gates” Published in: 2022 2nd International Conference on Intelligent Technologies (CONIT) INSPEC Accession Number: 21992421
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• Journal | Published On : 01-11-2021
  Vasundara Patel K S, Tulasi Naga Jyothi Kolanti
  “Design of Ternary Subtractor using Multiplexers”. Published in: Circuit world. 2021
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• Journal | Published On : 26-04-2021
  A. Rajagopal; K. Karibasappa; K.S. Vasundara Patel
  Hardware implementation of a modified SSD LDPC decoder, International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 14, No. 3, 2021
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• Journal | Published On : 16-10-2020
  Tulasi Naga Jyothi Kolanti, Vasundara Patel K S
  Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques. Inter national Journal of Circuit Theory and Application.
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• Journal | Published On : 24-04-2020
  A. Rajagopal, K. Karibasappa, Vasundara Patel K.S.
  Study of LDPC decoders with quadratic residue sequence for communication system
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• Journal | Published On : 03-02-2020
  Shruthi G, Vasundara Patel K S, Abhilash P.
  Beyond Binary, Beyond CMOS Implementation of TCAM Array
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• Conference | Published On : 21-11-2019
  M. Manjunath, K. S. Vasundhara Patel, N. A. M. Krishnan
  Mixed signal block for resistance calibration and matching
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• Conference | Published On : 21-11-2019
  Rakshith Saligram, Abhilash P, Vasundhara Patel K S
  Realization of multi-valued logic combinational circuits on fully depleted silicon on insulator (SoI)
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• Conference | Published On : 21-11-2019
  Shruthi G ; Abhilash P ; Vasunadara Patel K S
  Design of content addressable memory
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• Conference | Published On : 21-11-2019
  Rakshit saligram, Tulasi Naga Jyothi Kolanti, Vasundara Patel K.S.
  Quaternary Digital Circuits design using Carbon Nano Tube FETs
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• Conference | Published On : 21-11-2019
  Satish M N, Vasundara Patel K S
  High Performance FinFET based Inverter using Self Controlled Voltage Level Technique
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• Conference | Published On : 21-11-2019
  Raghuram Shivram; K. S. Vasundhara Patel; B. G Prasad
  Autonomous Biasing Circuit for GaN RF Amplifiers
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• Conference | Published On : 21-11-2019
  Vasundhara Patel K.S; Bhavana R
  Design and Verification of Wishbone I2C Master Device
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• Conference | Published On : 21-11-2019
  Niranjan S, Shanmukha Sandesh, Vasundara Patel K S,
  A Novel Design of Ternary Level SRAM cell using CNTFET IEEE International Conference on Networking embedded and Wireless Systems-2018(ICNEWS 2018),21 November 2019
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• Journal | Published On : 07-07-2019
  Lavita Floria Vas, Dr. Vasundara Patel K S
  CAN Based Data Acquisition and Data Logging System for Vehicular Communication
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• Journal | Published On : 02-06-2019
  Rajagopal Anantharaman, Karibasappa Kwadiki, Vasundara Patel K S
  Hardware implementation analysis of min-sum decoders
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• Conference | Published On : 24-04-2019
  Namboodiri Akhil M. M. Krishnan, K. S. Vasundhara Patel, Manjunath Jadhav
  Comparative Study Of Gm/Id Methodology For Low Power Applications, Emerging Research in Electronics, Computer Science and Technology, pp 949-959.
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• Conference | Published On : 05-01-2019
  Satish Masthenahally Nachappa, Vasundara Patel K S
  Power Reduction in FinFET Half Adder using SVL Technique in 32nm Technology, Conference: 2019 4th MEC International Conference on Big Data and Smart City (ICBDSC), IEEE Proceedings
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• Conference | Published On : 06-12-2018
  Satish Masthenahally Nachappa, S. Jeevitha, K. S. Vasundara Patel
  Comparative Analysis of Digital Circuits Using 16 nm FinFET and HKMG PTM Models, Future of Information and Communication Conference FICC 2018.
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• Journal | Published On : 09-10-2018
  A Rajagopal, K. Karibasappa, K.S. Vasundara Patel
  FPGA Implementation of SSPA decoder
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• Conference | Published On : 24-06-2017
  A. Rajagopal; K. Karibasappa; K. S. Vasundara Patel
  Design of SPA decoder for CDMA applications 23-24 June 2017
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• Conference | Published On : 21-02-2017
  A. Rajagopal, K. Karibasappa, K.S. Vasundara Patel
  FPGA implementation of logarithm of a number to base 2, Published in 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
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• Journal | Published On : 16-01-2016
  Poornima Baliga M, Vasundara Patel K S
  A Design Implementation of Single Stage Amplifiers using HEMT Technology
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• Journal | Published On : 13-04-2015
  Rajagopal.A, Karibasappa.K, Vasundara Patel K.S
  FPGA implementation of Modified Turbo encoder
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• Journal | Published On : 04-11-2014
  Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon
  Schmitt Trigger Based SRAM Using Finfet Technology- Shorted Gate Mode
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