Dr. VASUNDHARA PATEL K S

Dr. VASUNDHARA PATEL K S

Professor

Ph.D

vasu.ece@bmsce.ac.in

Research Interests: Multi-valued logic circuit Design, Carbon Nano Tubes, Graphene semiconductors, GaN, Analog and Mixed signal Circuits, Physical design, Digital Circuit Design

About

I have a total experience of 23 years which includes experiences in Industry, Academia and Research. Organized numerous workshops, guest lectures, Industry interactions, Internships for professional development of the department with industry collaboration, also Coordinating with Adjunct Faculty from industries to get associated with all activities of the department. Involved in setting up of state of the art labs for VLSI Design and Embedded Systems in association with TEQIP-2 and Electronics Sector Skill Council of India (ESSCI). Established Centre of Excellence in VLSI & Embedded System In Association with Electronic Skill Council of India (ESSCI) and India Electronic Semiconductor Association (IESA) at BMSCE. Convener and TPC Chair, International Conference on Networking, Embedded and Wireless Systems (ICNEWS -2018). I am interacting with outside world as Session chair, Technical project evaluator, doctoral committee member, BOE member also as resource person. Program Coordinator for PG ‘VLSI Design and Embedded Systems’ as well as PG NBA activity. I have published over 50 research papers, My current research includes LNA design in 45nm, GaN, Memory design in CNTFETs, FDSOI, Graphene semiconductors. Applied Patent for the Invention “Method and System for Arithmetic Circuits in quaternary Logic, and Capless LDO (Low Dropout Regulator) With Programmable Output Voltage.My hobbies are water/oil painting, Tanjore painting.

Education

  • Ph.D - ELECTRONICS ENGINEERING
    BANGALORE UNIVERSITY
    Passed Year: 2012 | Program Type: PartTime
  • M.TECH. - ELECTRONICS ENGINEERING
    B.M.S.C.E./V.T.U.
    Passed Year: 2002 | Program Type: FullTime
  • B.E. - ELECTRONICS AND COMMUNICATION ENGINEERING
    JNNCE/MYSORE UNIVERSITY
    Passed Year: 1989 | Program Type: FullTime

Selected Publications

  • Journal | Published On : 26-04-2021
    A. Rajagopal; K. Karibasappa; K.S. Vasundara Patel
    Hardware implementation of a modified SSD LDPC decoder, International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 14, No. 3, 2021
    Weblink
  • Journal | Published On : 16-10-2020
    Tulasi Naga Jyothi Kolanti, Vasundara Patel K S
    Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques. Inter national Journal of Circuit Theory and Application.
    Weblink
  • Journal | Published On : 24-04-2020
    A. Rajagopal, K. Karibasappa, Vasundara Patel K.S.
    Study of LDPC decoders with quadratic residue sequence for communication system
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  • Journal | Published On : 03-02-2020
    Shruthi G, Vasundara Patel K S, Abhilash P.
    Beyond Binary, Beyond CMOS Implementation of TCAM Array
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  • Conference | Published On : 21-11-2019
    Niranjan S, Shanmukha Sandesh, Vasundara Patel K S,
    A Novel Design of Ternary Level SRAM cell using CNTFET IEEE International Conference on Networking embedded and Wireless Systems-2018(ICNEWS 2018),21 November 2019
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  • Conference | Published On : 21-11-2019
    M. Manjunath, K. S. Vasundhara Patel, N. A. M. Krishnan
    Mixed signal block for resistance calibration and matching
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  • Conference | Published On : 21-11-2019
    Rakshith Saligram, Abhilash P, Vasundhara Patel K S
    Realization of multi-valued logic combinational circuits on fully depleted silicon on insulator (SoI)
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  • Conference | Published On : 21-11-2019
    Shruthi G ; Abhilash P ; Vasunadara Patel K S
    Design of content addressable memory
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  • Conference | Published On : 21-11-2019
    Rakshit saligram, Tulasi Naga Jyothi Kolanti, Vasundara Patel K.S.
    Quaternary Digital Circuits design using Carbon Nano Tube FETs
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  • Conference | Published On : 21-11-2019
    Satish M N, Vasundara Patel K S
    High Performance FinFET based Inverter using Self Controlled Voltage Level Technique
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  • Conference | Published On : 21-11-2019
    Raghuram Shivram; K. S. Vasundhara Patel; B. G Prasad
    Autonomous Biasing Circuit for GaN RF Amplifiers
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  • Conference | Published On : 21-11-2019
    Vasundhara Patel K.S; Bhavana R
    Design and Verification of Wishbone I2C Master Device
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  • Journal | Published On : 07-07-2019
    Lavita Floria Vas, Dr. Vasundara Patel K S
    CAN Based Data Acquisition and Data Logging System for Vehicular Communication
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  • Journal | Published On : 02-06-2019
    Rajagopal Anantharaman, Karibasappa Kwadiki, Vasundara Patel K S
    Hardware implementation analysis of min-sum decoders
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  • Conference | Published On : 24-04-2019
    Namboodiri Akhil M. M. Krishnan, K. S. Vasundhara Patel, Manjunath Jadhav
    Comparative Study Of Gm/Id Methodology For Low Power Applications, Emerging Research in Electronics, Computer Science and Technology, pp 949-959.
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  • Conference | Published On : 05-01-2019
    Satish Masthenahally Nachappa, Vasundara Patel K S
    Power Reduction in FinFET Half Adder using SVL Technique in 32nm Technology, Conference: 2019 4th MEC International Conference on Big Data and Smart City (ICBDSC), IEEE Proceedings
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  • Conference | Published On : 06-12-2018
    Satish Masthenahally Nachappa, S. Jeevitha, K. S. Vasundara Patel
    Comparative Analysis of Digital Circuits Using 16 nm FinFET and HKMG PTM Models, Future of Information and Communication Conference FICC 2018.
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  • Journal | Published On : 09-10-2018
    A Rajagopal, K. Karibasappa, K.S. Vasundara Patel
    FPGA Implementation of SSPA decoder
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  • Conference | Published On : 24-06-2017
    A. Rajagopal; K. Karibasappa; K. S. Vasundara Patel
    Design of SPA decoder for CDMA applications 23-24 June 2017
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  • Conference | Published On : 21-02-2017
    A. Rajagopal, K. Karibasappa, K.S. Vasundara Patel
    FPGA implementation of logarithm of a number to base 2, Published in 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
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  • Journal | Published On : 16-01-2016
    Poornima Baliga M, Vasundara Patel K S
    A Design Implementation of Single Stage Amplifiers using HEMT Technology
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  • Journal | Published On : 13-04-2015
    Rajagopal.A, Karibasappa.K, Vasundara Patel K.S
    FPGA implementation of Modified Turbo encoder
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  • Journal | Published On : 04-11-2014
    Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon
    Schmitt Trigger Based SRAM Using Finfet Technology- Shorted Gate Mode
    Weblink

Other Information

Professional Memberships: IEEE Senior member, IMAPS India, ISTE, IACSIT
Guiding Ph.d: 4
Grants fetched: TEQIP-2 funds (10 Lakhs) for Synopsis Software tools
25 lakhs funds from ESSCI for VLSI Labs



Patent Applied: Invention Titled “Method and System for Arithmetic Circuits in quaternary Logic".

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